General Description

The SAA7118 is a multistandard comb filter video decoder supporting various applications to capture analog video; it includes digitizing of component formats Y-PB-PR and RGB, and is providing high quality, optionally scaled video.

The SAA7118 is a combination of a four-channel analog preprocessing circuit including source selection, anti-aliasing filter and Analog-to-Digital Converter (ADC) with succeeding decimation filters from 27 MHz to 13.5 MHz data rate. Each preprocessing channel comes with an automatic clamp and gain control. The SAA7118 combines a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation control circuit.

It is a highly integrated circuit for desktop video and similar applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the color of PAL, SECAM and NTSC signals into ITU 601 compatible color component values. The SAA7118 accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources, including weak and distorted signals as well as baseband component signals Y-P_B-P_R or RGB. An expansion port (X port) for digital video (bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or a video phone codec. At the so called image port (I port) the SAA7118 supports 8-bit or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers.

The target application for the SAA7118 is to capture and scale video images, to be provided as a digital video stream through the image port of a VGA controller, for capture to system memory, or just to provide digital baseband video to any picture improvement processing.

The SAA7118 also provides a means for capturing the serially coded data in the Vertical Blanking Interval (VBI) data. Two principal functions are available:

• To capture raw video samples, after interpolation to the required output data rate, via the scaler
• A versatile data slicer (data recovery) unit

The SAA7118 also incorporates field-locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a field, or a set of fields. This prevents the loss of synchronization between video and audio during capture or playback.

All of the ADCs may be used to digitize a Vestigial Side Band (VSB) signal for subsequent decoding; a dedicated output port and a selectable VSB clock input is provided.

The circuit is I²C-bus controlled (full write/read capability for all programming registers, bit rate up to 400 kbit/s).

Key Features

Video acquisition/clock

• Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be used to convert e.g. VSB signals)
• Up to eight analog Y + C inputs, split as desired
• Up to four analog component inputs, with embedded or separate sync, split as desired
• Four on-chip anti-aliasing filters in front of the ADCs
• Automatic Clamp Control (ACC) for CVBS, Yand C (or VSB) and component signals
• Switchable white peak control
• Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz)
• Fully programmable static gain or Automatic Gain Control (AGC), matching to the particular signal properties
• On-chip line-locked clock generation in accordance with “ITU 601″
• Requires only one crystal (32.11 MHz or 24.576 MHz) for all standards
• Horizontal and vertical sync detection

Video decoder

• Digital Phase-Locked Loop (PLL) for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR
• Automatic detection of any supported color standard
• Luminance and chrominance signal processing for PAL B, G, D, H, I and N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM
• Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation, also with VTR signals
  • Increased luminance and chrominance bandwidth for all PAL and NTSC standards
  • Reduced cross color and cross luminance artefacts
• PAL delay line for correcting PAL phase errors
• Brightness Contrast Saturation (BCS) adjustment, separately for composite and baseband signals
• User programmable sharpness control
• Detection of copy-protected signals according to the Macrovision standard, indicating level of protection
• Independent gain and offset adjustment for raw data path

Component video processing

• RGB component inputs
• Y-PB-PR component inputs
• Fast blanking between CVBS and synchronous component inputs
• Digital RGB to Y-C_B-C_R matrix

Video scaler

• Horizontal and vertical downscaling and upscaling to randomly sized windows
• Horizontal and vertical scaling range: variable zoom to 1/64 (icon) (it should be noted that the H and V zoom are restricted by the transfer data rates)
• Anti-alias and accumulating filter for horizontal scaling
• Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy)
• Horizontal phase correct up and downscaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width)
• Two independent programming sets for scaler part, to define two ‘ranges’ per field or sequences over frames
• Fieldwise switching between decoder part and expansion port (X port) input
• Brightness, contrast and saturation controls for scaled outputs

VBI data decoder and slicer

• Versatile VBI data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North American Broadcast Text System (NABTS), closed caption, Wide Screen Signalling (WSS), etc.

Audio clock generation

• Generation of a field-locked audio master clock to support a constant number of audio clocks per video field
• Generation of an audio serial and left/right (channel) clock signal

Digital I/O interfaces

• Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to document “RTC Functional Specification” for details)
• Bidirectional expansion port (X port) with half duplex functionality (D1), 8-bit Y-C_B-C_R:
  • Output from decoder part, real-time and unscaled
  • Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible)
• Video image port (I port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and handshake signals
• Discontinuous data streams supported
• 32-word x 4-byte FIFO register for video output data
• 28-word x 4-byte FIFO register for decoded VBI data output
• Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 Y-C_B-C_R output
• Scaled 8-bit luminance only and raw CVBS data output
• Sliced, decoded VBI data output

Miscellaneous

• Power-on control
• 5 V tolerant digital inputs and I/O ports
• Software controlled power saving standby modes supported
• Programming via serial I²C-bus, full read back ability by an external controller, bit rate up to 400 kbit/s
• Boundary scan test circuit complies with the “IEEE Std. 1149.b1 – 1994″.

Downloads

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PCI_DVB_tuner_boards_and_Windows_drivers
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Datasheet

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