General Description

The 9-bit video input processor is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N and SECAM), a brightness, contrast and saturation control circuit, a multistandard VBI data slicer and a 27 MHz VBI data bypass.

The pure 3.3 V CMOS circuit SAF7113H, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the color of PAL, SECAM and NTSC signals into ITU-R BT 601 compatible color component values. The SAF7113H accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I²C-bus controlled.

The integrated high performance multistandard data slicer supports several VBI data standards:

• Teletext 625 lines: WST (World Standard Teletext) and CCST (Chinese teletext)
• Teletext 525 lines: US-WST, NABTS (North-American Broadcast Text System) and MOJI (Japanese teletext)
• Closed caption: Europe and US (line 21)
• Wide Screen Signalling (WSS)
• Video Programming Signal (VPS)
• Time codes (VITC EBU/SMPTE)
• High-speed VBI data bypass for Intercast application.

Key Features

• Four analog inputs, internal analog source selectors, e.g. 4 x CVBS or 2 x Y/C or (1 x Y/C and 2 x CVBS)
• Two analog preprocessing channels in differential CMOS style for best S/N-performance
• Fully programmable static gain or automatic gain control for the selected CVBS or Y/C channel
• Switchable white peak control
• Two built-in analog anti-aliasing filters
• Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or Y/C-signals are available on the VPO-port via I²C-bus control
• On-chip clock generator
• Line-locked system clock frequencies
• Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection
• Requires only one crystal (24.576 MHz) for all standards
• Automatic detection of 50 Hz and 60 Hz field frequency and automatic switching between PAL and NTSC standards
• Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and SECAM
• User programmable luminance peaking or aperture correction
• Cross-color reduction for NTSC by chrominance comb filtering
• PAL delay line for correcting PAL phase errors
• Brightness Contrast Saturation (BCS) and hue control on-chip
• Real-time status information output (RTCO)
• Two multifunctional real-time output pins controlled by I²C-bus
• Multistandard VBI data slicer decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), closed caption,
• Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE), etc.
• Standard ITU-R BT 656 YUV 4 : 2 : 2 format (8-bit) on VPO output bus
• Enhanced ITU-R BT 656 output format on VPO output bus containing:
  • Active video
  • Raw CVBS data for Intercast applications (27 MHz data rate)
  • Decoded VBI data
• Boundary scan test circuit complies with the “IEEE Std. 1149.b1 – 1994″ (ID-Code = 1 7113 02B)
• I²C-bus controlled (full read-back ability by an external controller and bit rate up to 400 kbit/s)
• Low power (< 0.5 W), low voltage (3.3 V), small package (QFP44)
• Power saving mode by chip enable input
• Detection of copy protected input signals according to the Macrovision standard; can be used to prevent unauthorized recording of pay-TV or video tape signals.

Block Diagram

Downloads

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digital_video_decoders_and_encoders_for_automotive_industrial_applications

Datasheet

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